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What Are The Best Bets When The Chips Are On The Table?

Governments worldwide are mobilizing to provide massive subsidies for the IC industry. The goal is to rejuvenate homegrown semiconductor fabrication ecosystems. In the US, the "Creating Helpful Incentives to Produce Semiconductors for America Act," or the CHIPS Act, has widespread support among lawmakers and will likely be funded before the end of this year. How should all this funding be spent?


Background


The rationale for semiconductor subsidies has been a lively debate topic over the last two years (see here or here as examples). Let’s recap briefly. Moore's law, the economic foundation for semiconductor manufacturing, has slowed considerably. Transistor costs on silicon used to drop by half when moved to a new technology node. But those economies are long gone. Over the past decade, transistor costs have started to increase. There are two reasons. First, as transistor gates continued to shrink below 20nm, the patterning technology (EUV lithography) became more complex and expensive. Second, the transistor gate changed from 2D planar to 3D structures approximately twelve years ago, requiring more fabrication steps and adding overall cost to the process.


Today, a fab capable of producing the most advanced semiconductors (~5nm) requires a capital investment of approximately $300k per WSPM (wafer starts per month) for a 100k WSPM facility. So, a 120k WSPM facility would cost roughly $30Bn in CAPEX. Process equipment costs (particularly EUV lithography tools) make up most of the investment. Depending on the particular fab, 40-60% of the wafer cost is a depreciation expense. Note that these are rough estimates, and every fab is different. For example, TSMC’s Arizona fab, which will be more expensive than the average, will reportedly cost $12Bn over the next decade and have an initial capacity of 20k WSPM.


Few applications (and fewer organizations) have enough volumes to amortize the CAPEX for a dedicated fab cost-effectively. So, most of the investment for these fabs comes from foundries that can add demand from many lower volume applications. But this concentrates capacity for advanced semiconductors in a handful of GigaFabs globally. In addition, industry consolidation has reduced the number of suppliers. As a result, the bargaining power has shifted considerably to foundries. TSMC illustrates the strong incentives to “go big” and achieve scale advantages here.


Two decades ago, the semiconductor demand from PC and mobile phone applications drove technology migration. Today, a more significant portion of semiconductor demand comes from everything as mundane as a washing machine to the driver-assist functions in your automobile. This broader penetration of semiconductor content has created a different problem. Since most of the cost of making an IC is in the depreciation costs of the equipment, fully depreciated fabs are much more cost-effective than new ones. The price points of older generation ICs make it almost impossible to justify building a new fab using older technology that has to depreciate over five years.


The result is escalating capital intensity at the leading edge and the trailing edge has restructured the industry.


The US CHIPS ACT


The origin of the US CHIPS act began with the DoD and the concern about access to leading-edge IC manufacturing technology from trusted sources. As the industry consolidated, there were few suppliers left. The need became urgent once Intel fell behind TSMC in fab processing capability. Recent geopolitical tensions with China, semiconductor shortages, and full-scale lobbying efforts by the SEMI organization have won legislative support.


The two-part US CHIPS Act is ambitious. The first part includes legislation that earmarks roughly $39Bn over five years to incentivize IC production in the US. These funds will fill the immediate need and ensure that the US has a secure supply chain.


The problem, of course, is that military applications won't keep any of these new fabs fully utilized. Industry advocates counter that commercial applications will fill the void. Indeed, the current chip shortages are feeding the urgency for new capacity. But semiconductor cycles are typical. The US (and European, South Korean, and Japanese) desire for local semiconductor industries will eventually lead to overcapacity.


Moreover, although $39Bn earmarked in the US is a large sum of money, it is small compared to the average industry CAPEX of $100Bn per year over the last five years. So, what will happen in five years when the next technology node transition occurs? Or after the industry emerges from the industry glut due to the current expansion when AR/VR, IoT, 6G, and other new technologies emerge to drive the next cycle of IC demand?


Over the last few decades, semiconductor executives have made rational investment decisions to focus less on manufacturing chips and more on designing chips and amassing intangible capital (IP, design talent, and marketing knowledge). What exactly will the $39Bn in funding in the US accomplish if, ten years from now, semiconductor executives make the same rational investment decisions to pursue higher returns in other endeavors? Will governments around the world ante up again for another round of CAPEX funding? Will semiconductor industry funding become another geopolitical arms race?


If subsidies are to rejuvenate self-sustaining indigenous IC fabrication ecosystems, governments worldwide will have to make some calculated bets. And this is why the second part of the US CHIPS act is so important. In addition to the $39bn in incentive programs to Band-Aid over the immediate gap, the legislation includes $10.5bn for R&D programs. These programs include provisions for National Advanced Packaging Manufacturing Program (NAPMP) and a National Semiconductor Technology Center (NSTC).


Part of the current discourse is to use the R&D funds to "level the playing field" with state-sponsored research in other countries. The R&D will fund technology areas like AI, quantum computing, robotics, and material science. Industry veterans made persuasive arguments about various programs (university funding, prototype labs) worth funding in several recent informational sessions on the CHIPS Act. But none of these suggestions will matter if local semiconductor production cannot sustain itself for the long term.


A Moonshot Proposal? Maybe not


What is missing from the current discussion is how to use R&D funding to change the underlying economic structure of the semiconductor industry so that it can sustain itself with rational business investment decisions. It would be best to focus bets on manufacturing technologies that can prime the free market for a self-sustaining local semiconductor industry.


The US has consistently focused public funding on technology development at the expense of manufacturing. As a result, manufacturing in the US has often been left to private industry and nudged through incentive programs when necessary. The results speak for themselves. The US government has a storied history of seeding emerging technologies for long-term growth (i.e., ENIAC, Navstar GPS, and ARPANET, to name a few). The record is spotty, however, for supporting regional manufacturing (i.e., Solyndra). In contrast, other countries like Japan have understood the importance of making manufacturing technology investments.


Changing the economic structure of the semiconductor industry begins with CAPEX. To keep up with whatever remains of Moore's law, process equipment costs (and EUV tools in particular) have escalated to the point where the minimum efficient scale is too high for all but a few large companies. It may be possible to redesign semiconductor process equipment so that a large fab downscales to more efficient production volumes that match distributed end demand. A smaller "PicoFab" would have lower CAPEX costs and proportionally lower throughput capacity. A PicoFab would maintain the same (or similar) CAPEX to throughput ratio as larger fabs (~$300k/WSPM in 2021) so that the cost per chip is the same (or similar). But instead of building a 100k WSPM fab for $30Bn, a PicoFab would have a capacity of 1k WSPM for $300M CAPEX.


There are historical examples from which to draw case studies. The rise of mini steel mills in the early 1980s provided an alternative to the large steel plants. Mainframe copiers in the 1960s located in a central back-office gave way to the desktop printer and allowed anyone to access printing. The current rise of 3D printing promises to provide the same disruption to the plastic injection molding industry.


There is nothing especially novel about downscaling infrastructure. A "PicoFab" is nothing more than a restatement of "lean manufacturing" or "flow" processes. PicoFabs emphasize process flow manufacturing over standard batch processing methods. The concept has a long tradition in manufacturing industries starting with Henry Ford, Frank Woollard, Edward Demming, Taiichi Ohno, and many others. It is the basis for the famous Toyota Production System (TPS). Fourteen years ago, Clayton Christensen, the renowned Harvard Business School professor, proposed a similar vision for the semiconductor industry. At the time, Mr. Christensen limited his scope using existing toolsets. But the concepts are as timely today as they were back then.


In Japan, the Minimal Fab consortium has already demonstrated the viability of a scaled-down fab. The Minimal FAB consortium was born out of the National Institute of Advanced Industrial Science and Technology (AIST). The organization developed a modular wafer manufacturing process with low capital costs (<$1M) and low throughput (~50 WPM). To do this, the group redesigned every fab process equipment to minimize cost and footprint. The feature sizes that can be patterned are coarse (0.8um), and the fab equipment uses custom 0.5" wafers. With these limitations, the Minimal Fab toolset is more appropriate for an R&D lab environment designing power MOSFETS or MEMs sensors. However, despite these drawbacks, the consortium has demonstrated the path forward. The process and tools were featured in the IEEE Heterogeneous Integration Roadmap 2021 Edition in the Aerospace and Defense section as a long-term (5-10 year) goal.


Optimizing CAPEX costs to match the distributed demand would allow the industry to move away from the scale advantages of a handful of GigaFabs. PicoFabs would lower entry barriers and enable more suppliers to maintain a fab. It would disperse IC manufacturing capability rather than consolidate it into a few big foundries, diffusing the domestic knowledge base for a manufacturing workforce. The same CAPEX/throughput ratio (or even slightly higher) helps fabricators to "pay as you grow" and reduce the overall investment risks. Finally, the military would access advanced semiconductor technology without depending on large sole-source suppliers.


It is impossible to design a Picofab today with a EUV lithography machine that costs around $150M. EUV lithography has a long and tortuous 20-year development history. The costs of EUV escalated as engineers strived to meet high-volume manufacturing requirements with complex sources and optics. Only one supplier, ASML, survived the high-stakes, high-tech development. Could designing away from batch processes to lean flow processes have offered a lower-cost design path for EUV? Maybe.That is hard to determine because you can't fairly assess counterfactual design paths. If not, next-generation lithography (NGL) like nano-imprinting or self-directed assembly may offer avenues for scaling down costs.


There will be other equipment design challenges as well. Developing a state-of-the-art nm scale PicoFab isn't easy, but the upsides are worth the risks. Semiconductor manufacturing has evolved to where suppliers have to commit enormous investments to stay competitive. Governments should use their resources to change the economic structure so that an indigenous ecosystem can thrive for the long term. PicoFabs may achieve that goal.


Final Thoughts


Semiconductor equipment makers, material providers, and support industries have the most to gain directly from the CHIPS act. But, the near-term $52Bn boost in the US (along with funding from other regions) to shore up the current ecosystem will have trickle-down effects on the whole electronic supply chain. This post offers a case for investing a portion of the R&D funds to designing smaller fabs that align better with distributed demand. Regardless of whatever objectives governments finally decide upon, these funding initiatives are a generational opportunity for the tech hardware supply chain. Therefore, business planning around these funding initiatives is imperative. RCD Strategic Advisors can help organizations assess and capitalize on these emerging funding opportunities.

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